This description relates to managing cache partitions based on cache usage information.
Many modern processors support hierarchical cache systems with multiple levels of cache, including one or more levels within the processor or within each core of a multi-core processor, and one or more levels external to the processor or cores, up to a last level cache (LLC) that is accessed just before main memory is accessed. At each level of the hierarchy, the cache stores copies of a subset of data to speed access to that data by the processor relative to the speed of a higher level cache (or relative to the speed of the main memory for the LLC). Lower level caches are closer to the processor (or core), whereas higher level caches are further away from the processor (or core). The LLC is typically shared by all of the cores of a multi-core processor. At each level, the cache system will load blocks of data into entries and evict blocks of data from entries in units of “cache lines” (also called “cache blocks”). Each cache line includes a number of “words” of data, each word consisting of a predetermined number of bytes.
A technique called “cache partitioning” (also called “cache allocation”) involves managing the way in which a particular cache is shared among multiple entities. For example, these entities may be different cores and the particular cache that is shared among the cores may be the LLC. In some examples, the management involves limiting a particular core to allocating new cache lines only within a particular assigned region of the LLC. By doing so, the cache will still be able to access data upon a hit in any region, but is limited to allocating (and if necessary evicting) data upon a miss only in its assigned region.